In microelectronics, the term interconnection is often used to describe a structure or a method of electrically connecting an active device such as a semiconductor, capacitor or a laser to a ceramic substrate or an organic board. One type of interconnection called hard or semipermanent, uses a low melting solder alloy. This is in contrast to a removable connection, such as pins and sockets.
Flip chip joining is a major sub-set within the area of solder interconnection. In flip chip joining, the electrical and physical connection is established between a ceramic substrate or organic board and a circuitized silicon chip, by joining corresponding terminals on the silicon and ceramic substrate or organic board by means of solder balls or columns. In all following discussions, the term "substrate" is used to denote either a silicon chip, a ceramic substrate or an organic board. The solder material for the ball is usually formed at the terminal metallization on either device or substrate and sometimes on both. The fabrication of soldered terminals is an important manufacturing process for microelectronics.
In applications where the quantity of solder in the solder interconnection is less critical and the features are relatively large (on order of a millimeter), dip, screen or spray soldering can be used. In critical applications where the volume and composition of solder need to be controlled tightly (less than 25% variation), solder terminal is fabricated by either evaporation of solder through a metal mask or resist mask, or plate up of solder through a resist mask. In general, the solder terminal on a substrate can be considered to be made of two parts, one a metallized layer referred to as terminal metallization, and the other a body of joining material (usually a solder). A separate terminal metallization is usually required since interconnection metals such as aluminum, chromium, molybdenum, tungsten etc., used for wiring on devices and substrates are not suitable since they are not easily wetted by and do not chemically react with solder in a controlled manner. U.S. Pat. No. 3,633,076 teaches a solder interconnection, in which the metallization requirements of a solder terminal are listed as electrical conductivity, adhesion/mechanical stability, ease of deposition and photo-processing, solderability and material stability in processing. U.S. Pat. No. 3,633,076 further teaches the use of a three layer metallization on a semiconductor, in order to satisfy these several opposing requirements. These requirements continue to be valid even now; however, additional new requirements have emerged for very large scale integrated devices. Some of the new requirements are, very high number of terminals (for increased number of inputs/outputs), precise placement of terminals, high mechanical stability (such as stress and adhesion) and low defect levels. For example, the stress due to terminal metallization has been found to result in formation of cracks in the thin insulating film underneath the metallization (Bhattacharya et al. U.S. Pat. No. 4,434,434). U.S. Pat. No. '434 teaches that a graded layered terminal metallization can reduce crack formation in the underlying brittle insulating film. Herdzik et al. (IBM Technical Disclosure Bulletin, p. 1979, vol. 10, No. 12, May 1968) discuss the use of overlying Al with Cr, Mo or W to prevent alloying of Al with solder when solder is reflowed. Leonard and Revitz (IBM Technical Disclosure Bulletin, p. 1121, vol. 13, No.5, October 1970) discuss the use of oxidized chromium as a barrier for use in solder terminals in conjunction with a phased Cr-Cu layer. Dalal and Jaspal (IBM Technical Disclosure Bulletin, p. 1005, vol. 20, No. 3, August 1977) describe a process of co-depositing Cr and Cu by evaporation to form a phased Cr-Cu layer. The Cr-Cu phased layer, which consists of mechanically interlocked Cr and Cu grains, has shown good adhesion to both the underlying Cr layer and to the overlying copper and copper intermetallic layer. Gardner et al (U.S. Pat. No. 4,840,302) teach the use of Cr-Ti alloy layer, instead of either Cr or Ti alone, as an adhesion layer to an organic insulator on which the terminal is formed. The U.S. Pat. No. '302 invention claims to reduce interface fractures when solder terminal is formed over an organic insulator.
There are other teachings that are specific to the manufacturing process of the solder terminal. The technical review article entitled "Solder Bump Fabrication by Electrochemical Method for Flip Chip Interconnection", by Kawanobe et al., (CH1671-7 IEEE, 1981 pp. 149-155), summarizes several alternate methods of forming solder bumps and underlying metallization. U.S. Pat. No. 5,162,257 issued to Edward K. Yung, teaches a process for fabricating a solder bump. In the U.S. Pat. No. '257 process, blanket metal layers (including copper) are formed over a substrate with the topmost layer being a patterned solder dam layer such as chromium (solder dam is a material that solder does not wet on melting). Regions of solder accumulation are formed on the substrate and the solder is reflowed to react with copper not covered by solder dam layer. This is followed by etching away the solder dam layer and other metallization layers using the solder and the intermetallic layer as an etch mask. U.S. Pat. No. 5,268,072, assigned to the assignee of the present invention, teaches a combination of wet and dry etch methods to form a graded or stepped edge profile of a three layer metallization Cr/Cr-Cu/Cu.
Each of the prior art teachings reviewed above, attempts to provide a solution to a specific problem encountered in their solder fabrication and use. However, none of the solutions appears to permeate across different applications. This is because, even though most interconnection terminal requirements are common to all uses, there are requirements that are unique to each use. Further, it is quite apparent that solder terminal formation technology is not easily predicted and experimental verification is often required for validation of any change in metallization or process. A primary objective of the present invention is to achieve a higher manufacturing yield and improve reliability of solder terminal and at the same time extend the process to form smaller and greater number of solder terminals on large substrates (e.g. 200 mm Si wafer) at reduced cost. It will become apparent from follow on specific discussions in the detailed description section, that many of the prior inventions do not adequately meet this primary objective of the present invention.